In testing of embedded systems, In-Circuit Emulation (ICE) is a technique that is used to debug embedded software running on one or more processors. In ICE, embedded software is typically debugged using a debugging infrastructure (e.g., using a debugger such as the GNU Debugger (GDB)). In ICE, components of the processor can be connected to a JTAG infrastructure, so that the debugger can access the components in order to gain knowledge of the remote program execution, and modify the remote program execution as needed. For example, the debugger may gain knowledge of registers (e.g., state and user registers), watchpoints, memory banks, clock control blocks, and other elements. While this provides a powerful mechanism for debugging software in its final environment, it is inhibited by the actual features of JTAG. For example, a typical ICE for a given processor core may need to access dozens of elements, and existing embedded designs may be composed of a large number of processor cores. As a result, efficient handling of JTAG operations is important, and presents a difficult problem given the considerable number of accesses needed in order to perform even the most simple of debug operations.
The existing JTAG-based ICE capabilities are deficient in a number of ways. First, existing ICE solutions require use of only one JTAG ICE interface at a time (or require special isolation logic for each processor core in order to enable multiple ICE interfaces to co-exist on the same target board). Second, existing ICE solutions rely heavily on Test Generation Tools (TGTs) for the handling of JTAG operations, which, in turn, rely heavily on user input in order to specify the topology of the scan chain surrounding the processor core. In fact, in existing ICE solutions, JTAG operations can be done only at the vector level, where there is no knowledge of the device internals. Third, existing ICE solutions typically rely on boundary scan access in order to access components of the target board, thereby requiring generation of complete testing vectors regardless of the testing being performed and, further, requiring retargeting of testing vectors when multiple devices are present within the boundary scan chain. As a result of such deficiencies, the TGT must maintain a complete, yet simplified, model of the system in order to be able to generate the required vectors and to interpret and decode the results. Disadvantageously, this requires a considerable amount of computational power, thereby limiting the scalability of the solution, especially for resource-constrained embedded approaches. Furthermore, the embedded controller can only perform basic input/output solutions and must make reference to a powerful host computer in order to run the TGT, and the interface with the TGT is usually vendor dependent and proprietary, thereby resulting in additional costs and loss in flexibility. Thus, existing ICE solutions make it virtually impossible to support multiple instances of ICEs.
The existing ICE capabilities are further deficient in that they cannot efficiently support multiple processor cores concurrently. In existing ICE solutions, in order to support ICE for multiple processor cores concurrently, a substantially more complex TGT, and associated model, is required in order to support coordination of command requests by each of the ICE instances running on the host machine. This involves a substantial and daunting task of retargeting based on the perspective of the entire scan chain that could change in its topology between each scan operation, i.e., the data sent to the target hardware is a variable length bit stream between each scan operation. This is not easily accomplished by existing TGTs that assume fixed length bit stream representations of data vectors to be applied to and recovered from the scan chain of the target hardware. While existing ICE capabilities are deficient in that they cannot efficiently support multiple processor cores concurrently, a potential solution for accessing multiple processor cores within a single target processor is the IEEE 1149.7 standard, which proposes a standardized ICE-JTAG interface to each processor core which can be used by debuggers to access the target processor. Disadvantageously, however, the complexity involved in handling vectors through the TGT seriously limits the features that may be implemented with the IEEE 1149.7 standard, including completely excluding support for concurrency.